1. Field of the Invention
The present invention relates to a received-data processing system for use in a data transmission system, LAN (Local Area Network) and the like in which computers or various control apparatuses distributed in different locations are mutually connected by a common transmission path for mutual data exchange. More particularly, this invention pertains to a received-data processing system capable of improving the data transmission rate.
2. Description of the Related Art
Today, due to the development of factory automation, there is a tendency of constructing a high-function, high-performance continuous process control system which has intelligent machines, such as a computer, PC (Programmable Controller), and DCS (Distributed Control System), connected to a common transmission path to build a network, exchanges information, such as production information including a manufacturing entry and product result, manufacturing program data and process control data, and monitor data, among these multiple machines, and executes decentralized control and supervisory control of the entire system. This type continuous process control system shares the supervisory data and control data which are to be exchanged among multiple machines, thus ensuring efficient decentralized control in individual machines and supervisory control of the entire system.
A typical data transmission system employed in information exchange among individual machines is a one-to-one type in which each machine transmits information while personally specifying another machine and acknowledges the reception of information from the destination. Due to the troublesome procedures and delayed processing speed, however, this one-to-one data transmission system has recently been replaced with a broadcasting or multicasting data transmission system, i.e., a data transmission system of a broadcast type. In this broadcast type data transmission system, each machine periodically transmits data and other machines receive the periodically on-coming monitor/control data. The monitor/control data is stored in a common memory having a specific memory address common to the individual machines, renewing the latest data. High-speed and effective N-to-N type information exchange is executed in this manner, and decentralized control for each machine and the supervisory control of the entire system are realized. Examples of such a data transmission system are a data transmission system as disclosed in Published Examined Japanese Patent Application No. 64-8501 and a network system employing a token-passing bus system as disclosed in Published Unexamined Japanese Patent Application No. 1-157143.
Referring to FIG. 1, the construction of a LAN system to be employed in the conventional continuous process control system will be described below. In this system, multiple nodes 1.sub.1 to 1.sub.n, such as control machines, are connected at proper intervals to a common transmission path L. These nodes 1.sub.1 -1.sub.n each have a common memory CM incorporated. A node having an authorization to use the transmission path broadcasts or multicasts the necessary information within a predetermined period of time, and gives the authorization to the next node upon each passage of the predetermined period of time. In other words, this system uses a media access control system. Although a loop network is constructed in FIG. 6, there may be a bus network having individual nodes 1.sub.1 -1.sub.n connected in a bus form, or a star network having the nodes connected in a star form.
The media access control systems include IEEE (Institute of Electrical & Electronics Engineers) 802.5 system to be applied to the loop network, an FDDI system standardized by American National Standards Institute (ANSI), IEEE 802.4 to be employed in the bus or star network and standardized by the IEEE. All of these systems are a token-passing type in which individual nodes exchange a frame called "token" with one another to give the transmission right to a proper node, so that multiple nodes do not simultaneously have the transmission permission at the same point of time. The node having received the token transmits data within a predetermined period of time. From the total number of nodes and the set times for the individual nodes, therefore, each node can therefore compute the maximum time that it has to wait to transmit data. Further, the individual nodes can surely send data in accordance with the predetermined order, and can surely access the transmission path.
In the LAN system shown in FIG. 1, each of the nodes 1.sub.1 to 1.sub.n broadcasts or multicasts a data frame, including its own output data as shown in FIG. 2, to the other nodes. Referring to FIG. 2, PA is a preamble, SSAP is a source service access point, SD is a start delimiter, FC is frame control, DA is a destination address, SA is a source address, DSAP is a destination service access point, C is an information command, WN is an information word number, DATA.sub.0 -DATA.sub.n are data, and FCS is a frame check sequence.
When the other nodes receive a data frame intended for the respective node, the data frame is stored at a specific common memory address in the common memory CM. The node having the authorization to use the transmission path gives the token frame to the next node when a predetermined period of time is elapsed. The node receiving this token frame has the right to use the transmission path for a predetermined period of time, and likewise transmits the data frame. Accordingly, all the nodes 1.sub.1 -1.sub.n share the same data in the common memory CM. FIG. 3 illustrates one example of a train of frames on the transmission path, which are transmitted by the individual nodes 1.sub.1, 1.sub.2, . . . , 1.sub.n in the order of the data frame DF.sub.1 followed by the token frame TK, DF.sub.2 followed by the token frame TK, and so forth, within a predetermined transmission period T.
The nodes 1.sub.1 -1.sub.n each have the hardware configuration as shown in FIG. 4. When one node having the authorization to use the transmission path, for example, the node l.sub.1, transmits the data frame shown in FIG. 2, each of the other nodes 1.sub.2 -1.sub.n receives the data frame at a transceiver circuit 21 and sends a received output 22 to a token passing receive and transmission control circuit 23. The control circuit 23 in each node checks the DA field in the received data frame to determine whether or not the received data is intended for that node. More specifically, if the node designating address, broadcasting address or multicasting address in the DA field in the data frame designates that node as the addressee, the control circuit 23 determines that the received data is intended for that node, and fetches the data frame in. When the control circuit 23 completes the reception of the data frame, a DMA (Direct Memory Access) control circuit 24 extracts the received data in the fields from the FC field to FCS field from the data frame, and stores the data in a receive buffer 25. At this time the received data is stored in the receive buffer 25 as shown in FIG. 5A or 5B. FIG. 5A illustrates the stored status of the receive buffer 25 in the case of the proper or normal data reception, and FIG. 5B the stored status of the buffer 25 when there is a reception error. In either case, the field length of the received data is "64." In these diagrams, STS (Status) is status information which indicates whether the reception has properly completed or a reception error has occurred, and LN (Length Number) represents the total quantity of data stored in the receive buffer 25.
A receive and transmission control processor 26 processes the received data upon reception of a data frame reception end signal 27. The processing of the received data is to Judge if the DSAP field, SSAP field and C field in the received data stored in the receive buffer 25 match with designated values. If matching is made, the WN field indicating the total quantity of data in the received data field and the ADRS (Address) field indicating the start memory address to store data in the common memory 28 are read out, and the WN value and ADRS value are set in the DMA control circuit 24. The DMA control circuit 24 in turn transfers received data DATA.sub.0 to DATA.sub.n in the receive buffer 25 to the common memory 28. The data stored in the common memory 28 is read out via a interface circuit 30 and utilized by a host equipment 29, such as a computer, PC or DCS. It is to be noted that a common bus memory control circuit is also provided, though not shown.
In FIG. 4, B1 is a buffer memory bus including a buffer memory data bus B1 1 and a buffer memory address bus B1.sub.2, B2 is a common memory bus having a common memory data bus B2.sub.1 and a common memory address bus B2.sub.2, and B3 is a host system bus.
In the above-described received-data processing system, after the received data frame is temporarily stored in the receive buffer 25 to complete the data reception, the values in the WN field and ADRS field in the frame are read out, and are transferred in DMA transmission to the associated address in the common memory 28 or the last storage section.
According to the conventional received-data processing system, therefore, there are the receive buffer 25 and the common memory 28 physically different from each other. Since the data frame is temporarily stored in the receive buffer 25, then finally stored in the common memory 28, data should be transferred from the former memory 25 to the latter memory 28. This results in longer time to process the received data, and thus restricts the data transfer performance of the entire system.
Even if one tries to increase the data transmission rate of the network system to enhance the transmission performance, the processing time involved in transmitting received data determines the data transfer performance of the common bus 33 between the receive buffer 25 and common memory 28. Improving the data transmission rate to some extent to enhance the transfer performance will therefore require complex hardware. In this case, there is also a limit to the performance.